library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ram_1w1r is
	generic(
	RAM_DATA_WIDTH	: integer:=8;
	RAM_ADDR_WIDTH	: integer:=8);
	port(
	a_clk	: in	std_logic;
	a_wr	: in	std_logic;
	a_addr	: in	std_logic_vector(RAM_ADDR_WIDTH-1 downto 0);
	a_wdata	: in	std_logic_vector(RAM_DATA_WIDTH-1 downto 0);
	b_clk	: in	std_logic;
	b_addr	: in	std_logic_vector(RAM_ADDR_WIDTH-1 downto 0);
	b_rdata	: out	std_logic_vector(RAM_DATA_WIDTH-1 downto 0));
end entity;

architecture behav of ram_1w1r is
type mem_Typ is array (2**RAM_ADDR_WIDTH-1 downto 0) of std_logic_vector(RAM_DATA_WIDTH-1 downto 0);
signal mem : mem_Typ;
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "M4K";
begin
	process(a_clk)
	begin
		if rising_edge(a_clk) then
			if a_wr = '1' then
				mem(conv_integer(a_addr)) <= a_wdata;
			end if;
		end if;
	end process;

	process(b_clk)
	begin
		if rising_edge(b_clk) then
			b_rdata <= mem(conv_integer(b_addr));
		end if;
	end process;

end architecture;
